QSC Q-SYS PS-1650G User Manual download pdf (Page 21)

1. Open the Quartus II project in the project directory for your development board type.

2. In Qsys, open top_system.qsys in the project directory for your development board type.

Add the JTAG-to-Avalon Master Bridge

The JTAG-to-Avalon master bridge acts as a bridge between the JTAG interface and the system's memory

tester.

1. In the IP Catalog select JTAG to Avalon Master Bridge, and then click Add.

2. In the parameter editor, click Finish to accept the default parameters.

3. Rename the instance to jtag_to_avalon_bridge.

4. Connect the jtag_to_avalon_bridge master interface to the memory_tester_subsystem slave

interface.

5. Set the jtag_to_avalon_bridge clk domain to sdram_sysclk.

6. Connect the jtag_avalon_bridge clk_reset interface to the ext_clk clk_reset interface.

7. Connect the jtag_avalon_bridge clk_reset interface to either the sdram reset_request_n interface (for

ALTMEMPHY-based designs), or sdram afi_reset interface (for UniPHY-based designs).

8. Connect the jtag_avalon_bridge master_reset interface to the memory_tester_subsystem reset

interface, and to either the sdram soft_reset_n interface (for ALTMEMPHY-based designs), or sdram

soft_reset interface (for UniPHY-based designs).

9. To disable the cpu_subsystem system, in the Use column, turn off Use, since you are replacing its

function with the bridge and System Console.

10.Save the jtag_to_avalon_bridge system.

Debug with System Console

The design example scripts test the memory in loops for different block sizes, that is, the number of bytes

to group together in a single instance of back-to-back reads or writes. The scripts also test the memory in

loops for different memory block trails, that is, the number of blocks by which the pattern reader trails the

pattern writer.

1. To download the programming file to your development board, in Qsys, click Generate > Generate.

2. Select the language for Create HDL design files for synthesis.

3. Click Generate. Qsys generates HDL files for the system and the .qip file, which provides the list of

required HDL files for the Quartus II compilation.

4. When Qsys completes the generation, click Close.

5. In the Quartus II software, click Project > Add/Remove Files in Project, and verify that the project

contains the top_system.qip.

6. Click Processing > Start Compilation. When compilation completes, click OK.

7. Connect the development board to a supported programming cable.

8. Click Tools > Programmer.

9. Check that the Programmer displays the correct programming hardware. Otherwise, click Hardware

Setup and select the correct programming hardware, and then click Close.

10.To program the device, click Start.

TU-01006

2015.05.04

Add the JTAG-to-Avalon Master Bridge

Qsys System Design Tutorial

Altera Corporation

Send Feedback

1 2 ... 16 17 18 19 20 21 22 23 24 25 26 27

Comments to this Manuals

No comments

QSC Q-SYS PS-1650G User Manual Page 21

Comments to this Manuals