QSC Q-SYS PS-1650G User Manual download pdf (Page 13)

• Create a Data Pattern Generator Qsys System on page 4

• Create a Data Pattern Checker Qsys System on page 8

• Qsys Tutorial Design Example

Create the Hierarchical Memory Tester System

The memory tester system includes several slave interfaces. However, the memory tester groups the

interfaces behind a pipeline bridge that exports a single slave interface to the top-level system. This

technique allows the top-level system to access all of the memory-mapped slave ports by reading and

writing to a single pipeline bridge slave interface. The bridge also adds a level of pipelining, which can

improve timing performance.

Figure 3: Memory Tester Design Interface

Avalon-MM Master

Avalon-MM Slave

Avalon-ST Source

Avalon-ST Sink

Pipeline Bridge

Pattern Generator

Subsystem

Data Checker

Subsystem

RAM Test

Controller

Pattern

Reader

Pattern

Writer

Avalon-MM Interface

Avalon-ST Interface

Legend

Memory Master

Components

TU-01006

2015.05.04

Create the Hierarchical Memory Tester System

Qsys System Design Tutorial

Altera Corporation

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QSC Q-SYS PS-1650G User Manual Page 13